1. Technical Field
The present disclosure generally relates to the manufacture and test of integrated circuits, including by way of example, Systems On Chips SOC.
2. Description of the Related Art
New integration technologies tend to offer a higher density of transistors and more rapid interconnections. By integrating heterogeneous circuits on a same chip to make a “system on chip”, it is possible to reduce the times and costs for designing and manufacturing such systems.
Thus, Systems On Chip SOC increasingly tend to gather into a same integrated circuit hardware components such as heterogeneous processor cores, specialized circuits, and memories, as well as a complex communication architecture called “Network On Chip” NOC, linking these components between them. Due to the increasing complexity of systems on chip, it is desirable to implement design, modeling and simulation tools allowing a system to be tested at different designing steps, so as to be able to validate the system at each of these steps. It is also desirable to be able to test a system or an integrated circuit once it is totally or partially embedded into a chip. Now, testing integrated circuits becomes more and more expensive and constitutes a great part of the total manufacturing cost of the circuit. To reduce the cost of these tests, additional circuits, called integrated testing circuits may be provided during the manufacture of the integrated circuit to perform these tests. These tests are usually called Built-In Self Tests BIST.
In addition, built-in self tests increasingly tend to allow the performances of the system to be analyzed. During an adjusting phase, these tests may be applied to an isolated part of the system. These tests may concern the sources of clock signals such as phase-lock loops PLL, frequency synthesizers, clock trees, interconnections between the different parts of the system, and also the noise generated by the parts of the system. Analyzing the integrity of signals may be performed by a frequency analysis, a parameter analysis S, a jitter analysis, etc. The integrity of the supply voltages of a system is a crucial point for high speed serial links, and in particular for memory interfaces. The supply voltages in an integrated circuit may be subjected to disturbances which importance may be linked to the length of the links supplying these voltages to the different parts of the integrated circuit. The supply voltages may also be subjected to variations resulting in particular from the activity of the various parts of the integrated circuit.
However, analyzing the integrity of supply voltages, which may be performed in the frequency domain, is highly complex due to the small amplitude of the oscillations appearing in the supply voltages. Generally, there is no metric means allowing the supply voltage integrity to be characterized.
It is however desirable to be able to test an integrated circuit so as to obtain significant and reliable information on the integrity of supply voltages of the integrated circuit.